1. Field of the Invention
This invention relates generally to a method and apparatus for routing die interconnections on a semiconductor die and, more specifically, to a method and apparatus for routing die interconnections using intermediate connection elements secured to a major surface of the die.
2. State of the Art
A typical integrated circuit (IC) or semiconductor die includes external connection points termed “bond pads” that are in electrical communication with integrated circuits formed in or on the active surface of the die. The bond pads are used to provide electrical connection between the integrated circuits and external devices, such as lead frames or printed circuit boards. The bond pads also provide sites for electrical testing of the die, typically by contact with probes, which send and receive signals to and from the die to evaluate the functionality of the die.
In a conventional die/lead frame assembly, the semiconductor die is attached to a die paddle of a lead frame using an adhesive or tape. The bond pads formed on the face of the die are typically electrically and mechanically attached to lead fingers terminating adjacent the periphery of the die using thin bonding wires of gold, aluminum or other metals or alloys. Other types of lead frames, such as so-called “leads over chip” (LOC) or “leads under chip” (LUC), dispense with the die paddle and support the die from portions of the lead fingers themselves.
Wire bonding is typically a process through which some or all of the bond pads formed on the face of the die are connected to the lead fingers or buses of a lead frame by thin bonding wires. The bonding wires comprise the electrical bridge between the bond pads and the leads of the packaged integrated circuit. A wire bonding apparatus bonds the bonding wires to the bond pads and to the lead fingers, typically using heat and pressure, as well as ultrasonic vibration in some instances. Following wire bonding, the lead frame and die are typically encapsulated in a plastic (particle-filled polymer) or packaged in a preformed ceramic or metal package. After encapsulation, the lead fingers are then trimmed and usually bent to form external leads of a completed semiconductor package in what is termed a “trim and form” operation.
Another wire bonding application may include chip-on-board (COB), where the back-side surface of a bare IC die is directly mounted on the surface of a substantially rigid printed circuit board (PCB) or other carrier substrate, and bond pads on the front-side or active surface of the bare die are then wire bonded to wire bondable trace pads or terminals on the surface of the PCB to interconnect circuitry in the die with external circuitry through conductive traces on the PCB. Likewise, wire bondable traces may be formed from a metal film carried on a flexible polyimide or other dielectric film or sheet similar to those employed in so-called TAB (tape automated bonding) lead frame structures. A die may be back-mounted on the flex circuit and the traces wire bonded to bond pads on the surface of the die.
A typical die bond pad is formed as a rectangle or square typically having an area of less than 104 μm2 and framed or bounded by a passivation layer on the face of the die. Bond pads are typically formed from a conductive metal such as aluminum and electrically connected to an underlying integrated circuit formed in or on the die. Usually a barrier layer and a polysilicon layer separate the bonding pad from an oxide layer of a silicon substrate in which the active semiconductor devices are formed. A passivation layer formed of a dielectric material (silicon dioxide, silicon nitride, polyimide, BPSG, etc.) or as a sandwich of different materials (e.g., silicon dioxide/silicon) covers the oxide layer, and the bond pad is embedded in the passivation layer. Such bond pads may be located generally along the peripheral edges of the die, inset from the edges a desired distance, or in one or more center rows. These bond pads are then typically wire bonded to a lead frame, thermocompression bonded to an overlying TAB tape or flip-chip bonded (with appropriate prior “bumping” of the bond pads) to a printed circuit board.
It is often desirable to interconnect various bond pads on a single semiconductor die in order to alter the input and/or output functionality of the die, such as when it is necessary to “wire around” defective portions of a die which is only partially functional. For example, a 16 megabit DRAM memory die may only demonstrate 11 megabits of functional memory under electrical testing and burn-in. Alternatively, it may be desirable for a die having a given input/output (bond pad) configuration to “look” to a particular lead frame or carrier substrate as if it were configured differently so that the die could be used with a lead frame for which it was not originally intended. Such “wire around” functions, where possible, are typically accomplished by interconnecting bond pads on the die through external circuitry in printed circuit boards or other carrier substrates to which the die is mounted. Where the desired input and/or output functionality configuration varies from die to die, a separately configured printed circuit board or other carrier substrate must be provided for each desired input and/or output functional configuration. Thus, it would be desirable to provide a relatively easy way of interconnecting selected bond pads on a single integrated circuit die without requiring the use of external circuitry in printed circuit boards and other carrier substrates.